In an information processing system, a dynamic random access memory (DRAM), or the like, is used as a working memory. The DRAM is usually a volatile memory in which stored content is lost when the power supply is stopped. Meanwhile, a non-volatile memory (NVM) has gained popularity in recent years. The non-volatile memory is roughly classified into a flash memory and a non-volatile random access memory (NVRAM). The flash memory handles data access that has a large unit in size. The NVRAM is capable of high-speed random access in a small unit. The flash memory is represented by a NAND flash memory. In contrast, exemplary non-volatile random access memories include a resistance RAM (ReRAM), a phase-change RAM (PCRAM), and a magnetoresistive RAM (MRAM).
Conventionally, when a page including a defect associated with memory access (defective page) is determined on such a non-volatile memory, the errors that occur in a write operation or an erase operation are counted. For example, there is proposed a storage apparatus that sends a notification of the number of errors generated by the write operation or the erase operation from a storage apparatus to a memory controller and that performs defect judgment on the memory controller (for example, refer to Patent Document 1).
Meanwhile, it is known that, in a certain type of non-volatile memory, distribution of errors caused by wear of a cell that undergoes repeated rewriting exhibits characteristics that vary depending on the storage state after the writing. For example, there is a known ReRAM in which an error caused by a reset operation that transitions the state from a low resistive state (LRS) to a high resistive state (HRS) is dominant (For example, refer to Non-Patent Document 1). Moreover, there is a known ReRAM in which an error caused by a set operation that transitions the state from the high resistive state (HRS) to the low resistive state (LRS) is dominant (for example, refer to Non-Patent Document 2).